1. Technical Field
The invention disclosed and claimed herein generally pertains to a method for managing flow control updates in a PCI Express (PCIE) environment. More particularly, the invention pertains to a method of the above type wherein a Credit Control Entity (CCE) receives credit count information that represents available storage capacity of receivers in the PCIE environment. Even more particularly, the invention pertains to a method of the above type wherein updates, derived by the CCE from the credit count information, are used to enable transmissions to the receivers.
2. Description of the Related Art
In a PCIE fabric environment, packet traffic is directed to virtual channels (VCs) by mapping packets with traffic class labels to corresponding VCs. Moreover, PCIE provides the capability of mapping multiple traffic classes onto a single VC. This is achieved by arranging for traffic flowing through a VC to be multiplexed onto a common physical Link, from Transmitters on the transmit side of the Link. Subsequently, the traffic is de-multiplexed into separate VC paths and directed to corresponding Receivers, on the receive side of the Link.
Within a PCIE switch, each of the VCs requires dedicated physical resources, such as RAMS, buffers or queues, in order to provide buffering or storage capacity. This is necessary to support independent traffic flows inside the switch. Accordingly, a PCIE environment is provided with a Flow Control (FC) mechanism, in order to prevent overflow of Receiver storage buffers and also to enable compliance with ordering rules. The Flow Control mechanism is used by a Requestor, that is, a device originating a transaction in the PCIE domain, to track the buffer space available in a Receiver that is on the opposite side of a Link. Such tracking is carried out by means of a credit-based Flow Control procedure, designed to ensure that a packet is transmitted only when a buffer is known to be available to receive the packet at the other end. This eliminates any packet retries, as well as associated waste of bandwidth due to resource constraints. Each virtual channel maintains an independent Flow Control credit pool. Flow Control information is conveyed between two sides of a Link, by means of Data Layer Link packets (DLLP).
Flow Control is generally handled by the Transaction Layer, in cooperation with the Data Link Layer, with the Transaction Layer performing Flow Control accounting for received Transaction Layer packets (TLPs). The Transaction Layer gates a Transmitter, based on available credits for transmission, in order to allow the Transmitter to send a TLP to a specified Receiver. In support of this Transmitter gating function, an initialization procedure is required, wherein Receivers must initially advertise VC credit values that are equal to or greater than certain pre-specified values. The number of credits allocated to a Transmitter is initially set according to the buffer size and allocation policies of the Receiver. As a succession of TLP transmissions occur, a count is kept of the credits being consumed. Before transmitting a given TLP, the Transmitter gating function must determine if sufficient credits are available to permit transmission of the given TLP. If the intended Receiver does not have enough credits to receive the TLP, the Transmitter must block the transmission of the TLP, possibly stalling other TLPs that are using the same virtual channel. The Transmitter must follow prescribed ordering and deadlock avoidance rules, which require that certain types of TLPs must bypass other specific types of TLPs when the latter are blocked.
Additionally, the credit accounting procedure tracks the count of the total number of credits granted to a Transmitter since initialization. This count may be incremented, as the Receiver side Transaction Layer makes additional received buffer space available by processing received TLPs. It would be beneficial to provide a central control that continually receives all the credit count information pertaining to each Receiver in a PCIE fabric. The central control could process such information, to provide flow control management throughout the PCIE fabric.